Welcome to my blog!
If you are looking for free open source SystemVerilog verification IPs, models, useful components for your testbench or you want to have a complete verification environment then you are in the right place.
Who am I?
I am Tiksan, Senior IC Design and Verification engineer. I have masters degree in electronics and 10+ years of design and verification experience with a lot of completed projects in audio, video, security and communication areas.
Why did I decide to open this blog?
Some time ago I had a project where the AMBA AHB verification IP was needed. And I was really surprised when I did not find any free verification IP in the internet. So I decided to do that.
I hope you will find some useful information here.