Welcome to my blog!

If you are looking for free open source SystemVerilog verification IPs, models, useful components for your testbench or you want to have a complete verification environment then you are in the right place.

Who am I?

I am Tiksan, Senior IC Design and Verification engineer. I have masters degree in electronics and 9 years of design and verification experience with a lot of completed projects in audio, video, security and communication areas.

Why did I decide to open this blog?

Several months ago I had a project where the AMBA AHB verification IP was needed. And I was really surprised when I did not find any free verification IP in the internet. So I decided to build a web site and share my verification IPs with you.

Why did I decide to create blog instead of static site?

As here I can have more communication with you. And your feedback will help me to improve my products to fit all your needs.

I hope you will find some useful information here and will enjoy reading my articles.