Avalon-MM Interface Verification IP

The Altera Avalon-MM Interface Verification IP (VIP) is a solution for verification the designs with Avalon-MM (Memory-Mapped) interface. The provided verification package includes master and slave verification IPs and integration examples. The VIP is fully compliant with protocol specification and can be very powerful tool to check, monitor and debug the Avalon MM protocol.

You can download the Avalon-MM Verification IP from Downloads page.


  1. Compliant to the Avalon Interface specification
  2. Operates as a Master or Slave
  3. Supports 1, 2, 4, 8, 16, 32, 64 and 128 bytes data block size
  4. Supports bus idle insertion between data frames
  5. Supports burst read and write
  6. Supports misaligned transfers
  7. Supports wait request and read data available
  8. Supports full random timings
  9. Easy integration and usage
  10. Free SystemVerilog source code


  1. Doesn’t support lock, debugaccess and begintransfer signals


  1. Download the Avalon-MM Verification IP and unpack it.
  2. If you want to run examples
    1. Go to the following folder: <unpack_dir>/avalon_mm_vip/examples/sim
    2. For VCS type the following command: vcs -f file_list.f -sverilog
    3. For QuestaSim10.0c type the following command: qverilog -f file_list.f
  3. Please read the Avalon-MM Verification IP User Manual.


If you have any questions please don’t hesitate to contact me.

You can also use article comments below to ask your questions, to report about bugs or to tell some ideas for future improvement. Your comments are always welcome!

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