The Avalon-ST Verification IP is a simple solution for verification of Altera Avalon Streaming source and sink interfaces. The provided Avalon-ST verification package includes master (source) and slave (sink) SystemVerilog verification IPs and examples. It will help engineers to quickly create verification environment end test their Avalon Streaming interfaces.
You can download the Avalon-ST Verification IP from Downloads page.
- Free SystemVerilog source code
- Easy integration and usage
- Compliant to Avalon Interface Specifications Ver1.2
- Operates as a Master or Slave
- Supports 1, 2, 4, 8, 16 and 32 bytes data block size
- Configurable endians (little endian or big endian)
- Supports wait states injection
- Supports full random “empty” value generation
- Supports full random timings
- Supports wrong start/end of packet insertion and detection
- Doesn’t support multiple channels
- Doesn’t support error signals
- readyLatency is fixed to zero
- Download Avalon-ST Verification IP and unpack it.
- If you want to run examples
- Go to the following folder: <unpack_dir>/avalonst_vip/examples/sim
- For VCS type the following command: vcs -f file_list.f -sverilog
- For QuestaSim6.4 type the following command: qverilog -f file_list.f
- Please read the Avalon-ST Verification IP User Manual.
If you have any questions please don’t hesitate to contact me.
You can also use article comments below to ask your questions, to report about bugs or to tell some ideas for future improvement. Your comments are always welcome!