The AMBA4 AXI-Lite Verification IP is an open source solution for verification of AXI-Lite master and slave devices. The provided AXI4-Lite verification package includes master and slave SystemVerilog verification IPs and examples. It will help engineers to quickly create verification environment end test their AXI-Lite master and slave devices.
You can download the AXI4-Lite Verification IP from Downloads page.
- Free SystemVerilog source code
- Easy integration and usage
- Compliant to AMBA4 AXI-Lite Protocol Version: 2.0
- Operates as a Master or Slave
- Supports 1, 2, 4, 8 and 16 bytes data block size
- Supports multiple outstanding transactions
- Programmable response type
- On the fly Read/Write response check
- Supports wait states injection
- Supports programmable retry and error insertion
- Supports full random timings
- Supports misaligned transfers
- Doesn’t support awprot and arprot signals
- Download the AXI4-Lite Verification IP and unpack it.
- If you want to run examples
- Go to the following folder: <unpack_dir>/axi4lite_vip/examples/sim
- For VCS type the following command: vcs -f file_list.f -sverilog
- For QuestaSim type the following command: qverilog -f file_list.f
- Please read the AXI4-Lite Verification IP User Manual.
If you have any questions please don’t hesitate to contact me.
You can also use article comments below to ask your questions, to report about bugs or to tell some ideas for future improvement. Your comments are always welcome!