AMBA4 AXI-Lite Verification IP

The AMBA4 AXI-Lite Verification IP is an open source solution for verification of AXI-Lite master and slave devices. The provided AXI4-Lite verification package includes master and slave SystemVerilog verification IPs and examples. It will help engineers to quickly create verification environment end test their AXI-Lite master and slave devices.

You can download the AXI4-Lite Verification IP from Downloads page.

Features

  1. Free SystemVerilog source code
  2. Easy integration and usage
  3. Compliant to AMBA4 AXI-Lite Protocol Version: 2.0
  4. Operates as a Master or Slave
  5. Supports 1, 2, 4, 8 and 16 bytes data block size
  6. Supports multiple outstanding transactions
  7. Programmable response type
  8. On the fly Read/Write response check
  9. Supports wait states injection
  10. Supports programmable retry and error insertion
  11. Supports full random timings
  12. Supports misaligned transfers

Limitations

  1. Doesn’t support awprot and arprot signals

Installation

  1. Download the AXI4-Lite Verification IP and unpack it.
  2. If you want to run examples
    1. Go to the following folder: <unpack_dir>/axi4lite_vip/examples/sim
    2. For VCS type the following command: vcs -f file_list.f -sverilog
    3. For QuestaSim type the following command: qverilog -f file_list.f
  3. Please read the AXI4-Lite Verification IP User Manual.

Support

If you have any questions please don’t hesitate to contact me.

You can also use article comments below to ask your questions, to report about bugs or to tell some ideas for future improvement. Your comments are always welcome!

12 thoughts on “AMBA4 AXI-Lite Verification IP

  1. Hi Tiksan,

    Thanks for providing this verification IP. I want to extend it for AXI protocol. Can you please give some suggestions?

    Thanks and regards,
    Chandan

  2. Hi Tiksan,
    In axi master interface you have written “clock alignment” as comment for one sequence.what does it mean .could you please tell about that a little bit more.
    ex:
    sequence sync_posedge; //clock alignment
    @(posedge clk) 1; //if I write 2 here instead of 1 what will happen?
    endsequence

    this sequence has been used in one task called clockalign().

    ex: task clockalign();
    wait(sync_posedge.triggered);
    endtask

    what is the difference between ifc.clockalign() and @ifc.cb . are they same?

  3. dear sir

    hi Tiksan thank for you. your website gives very much information
    i have download AXI4Lite. but i not able to findout dut can you provid for me

    thank you

  4. I have download axi4lite_vip from http://syswip.com/. When I try the examples, I got some timeout ERROR. I’m not sure is there a bug of this VIP?
    Following is my type command and error log:

    irun –f file_list.f

    ncsim> run
    Data In: Packet size is 21 bytes
    4932f8cf 590e0438 7c2394c7 86e19b56 efaf8bf0 f7
    Data Length is 21 bytes
    Address is 33088dcc
    #—–Check 1 Passed!!!
    #—–Check 2 Passed!!!
    Data In: Packet size is 1 bytes
    65
    Data Length is 1 bytes
    Address is e43c7e99
    #—–Check 3 Passed!!!
    #—–Check 4 Passed!!!
    Data In: Packet size is 23 bytes
    5ed4f162 499974f4 6c8e2140 c2769b7a b7a307ba c67c62
    Data Length is 23 bytes
    Address is f0142928
    #—–Check 5 Passed!!!
    #—–Check 6 Passed!!!



    Data In: Packet size is 43 bytes
    06c3f1c1 53332e44 535c10a9 ae7d4b8c 69b264cb 8bd2934d b6ae9040 afc352c4
    d461c204 883c55c6 8171a2
    Data Length is 43 bytes
    Address is f41c8cff
    #—–Check 51 Passed!!!
    #—–Check 52 Passed!!!
    Data In: Packet size is 32 bytes
    c6639fc3 3ceb1c0b 44977d4c 3ba09a72 b89b67bc eb644e65 7302fc3d a3759e2a

    Data Length is 32 bytes
    Address is 20bc3a7d
    #—–Check 53 Passed!!!
    #—–Check 54 Passed!!!
    Data In: Packet size is 31 bytes
    be966724 88c0d816 475a4361 e998b45b 220583be c6d30b21 52e78209 a68815
    Data Length is 31 bytes
    Address is 8c9889a5
    ERROR: Write address channel TimeOut Detected at sim time 100115
    ERROR: Write data channel TimeOut Detected at sim time 100115
    ERROR: Write response channel TimeOut Detected at sim time 100435
    ERROR: Write address channel TimeOut Detected at sim time 100435
    ERROR: Write data channel TimeOut Detected at sim time 100435
    ERROR: Not OK write response Detected at sim time 100475
    ERROR: Write address channel TimeOut Detected at sim time 100595
    ERROR: Write data channel TimeOut Detected at sim time 100695
    ERROR: Write response channel TimeOut Detected at sim time 100745
    ERROR: Write data channel TimeOut Detected at sim time 100785
    ERROR: Write response channel TimeOut Detected at sim time 100895
    ERROR: Write address channel TimeOut Detected at sim time 100895
    ERROR: Not OK write response Detected at sim time 100905
    ERROR: Write address channel TimeOut Detected at sim time 100965
    ERROR: Write response channel TimeOut Detected at sim time 101005
    ERROR: Write data channel TimeOut Detected at sim time 101005
    ERROR: Write data channel TimeOut Detected at sim time 101075
    ERROR: Write response channel TimeOut Detected at sim time 101195
    ERROR: Write address channel TimeOut Detected at sim time 101215
    ERROR: Write response channel TimeOut Detected at sim time 101285
    ERROR: Read address channel TimeOut Detected at sim time 101475
    ERROR: Read Data channel TimeOut Detected at sim time 101795
    ERROR: Read address channel TimeOut Detected at sim time 101795
    ERROR: Not OK read response Detected at sim time 101915
    ERROR: Read Data channel TimeOut Detected at sim time 102115
    ERROR: Read address channel TimeOut Detected at sim time 102115
    ERROR: Not OK read response Detected at sim time 102185
    ERROR: Read Data channel TimeOut Detected at sim time 102355
    ERROR: Read address channel TimeOut Detected at sim time 102355
    ERROR: Not OK read response Detected at sim time 102375
    #—–Check 55 Passed!!!
    #—–Check 56 Failed. Current Check has 2 errors
    Expected Packet: Packet size is 8 bytes
    00000000 00000000
    Result Packet: Packet size is 8 bytes
    00000000 00fc00fc
    Simulation complete via $finish(1) at time 102615 NS + 4
    ../testbench/test.sv:64 if(chk.CheckPkt(wrRespOut, wrRespExp) == -1) $finish;
    ncsim> exit

  5. Hello Tiksan,

    thanks for taking on the initiation to create open source verification IP. You have covered almost all the major interface protocols, which is quite helpful.

  6. Hi Tiksan,
    As per the documentation axi4lite_vip_user_manual.pdf on Pg 13, in order to use this VIP as a AXI Slave, one needs to substitute the placeholders for:
    AXI4Lite_s_env axi4lite = new(id_name, axi4lite_ifc_s, dataSize);

    In my top-level testbench I have used the following (part of the testbench code):
    axi4lite_s_if axi4lite_s_if_inst(); // instiantiate the interface

    initial begin
    // Create AXI4Lite_s_env class object
    AXI4Lite_s_env axi4lite = new(axi4lite_s, axi4lite_s_if_inst, 4);

    // Start AXI4-Lite Slave Environment
    axi4lite.startEnv();
    end

    But during compilation using VCS of Synopsys, I am geting the following error msg:
    Error-[IND] Identifier not declared te0630_top_tb.sv, 195
    Identifier ‘axi4lite_s’ has not been declared yet. If this error is not
    expected, please check if you have set `default_nettype to none.

    In the PDF it is said id_name is the name of the slave vip(string variable).
    So I have used ‘axi4lite_s’ due to the slave file “axi4lite_s.sv”.
    Can you please throw some light?

  7. Hello Tiksan,

    I need your help to understand the APB interface for my project . Do you have any material that can help me to understand the APB interface . I have seen your blog that is very helpful to get verification Ip .

    Thank you .

  8. Hi Tiskan,

    Thanks for making this piece of BFM opensource.
    It is simple, easy to understand and integrate in a design.

    I have successfully used the Master and Slave BFMs after connecting it to the Xilinx AXI (I configured it to behave as AXI4Lite) Interconnect IP. My AXI interconnect system is a part of an embedded uP extension design. After defining the memory map in the AXI Interconnect address decoder, from software, I can drive and monitor Master and Slave transactions.

    Hats-off to you for your contribution. It saved a lot of time for verifying my design.

    Best regards,
    Debayan

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