AXI4 Stream Protocol Verification IP

The AMBA4 AXI Stream Interface Verification IP (VIP) is a solution for verification the designs with AXI4-Stream interface. The provided verification package includes AXI4-Stream verification IP, Protocol Monitor and integration examples. The VIP is fully compliant with AXI4-Stream specification and can be very powerful tool to check, monitor and debug the AXI4-Stream protocol.

You can download the AXI4-Stream Verification IP from Downloads page.

Features

  1. Compliant to the AXI4-Stream specification
  2. Operates as a Master or Slave
  3. Supports 1, 2, 4, 8, 16 and 32 bytes data block size
  4. Supports up to 8 user bits per byte
  5. Supports bus idle insertion between data frames
  6. Supports full random timings
  7. Protocol monitor to find bus violations
  8. Easy integration and usage
  9. Free SystemVerilog source code

Installation

  1. Download the AXI4-Stream Verification IP and unpack it.
  2. If you want to run examples
    1. Go to the following folder: <unpack_dir>/axi4_stream_vip/examples/sim
    2. For VCS type the following command: vcs -f file_list.f -sverilog
    3. For QuestaSim10.0c type the following command: qverilog -f file_list.f
  3. Please read the AXI4-Stream Verification IP User Manual.

Support

If you have any questions please don’t hesitate to contact me.

You can also use article comments below to ask your questions, to report about bugs or to tell some ideas for future improvement. Your comments are always welcome!

5 thoughts on “AXI4 Stream Protocol Verification IP

  1. Hi Tiksan,
    Thanks for providing verification IP. can i get any ovm/uvm based verification ip. Because i wanted to implement ovm based verification ip for my M.S project. I have studied ovm concepts but i am in confusion that how to start.If you can help me please give a suggestion where can i find ovm based verification ip.

  2. Hi Prasad,

    I don’t have an OVM based verification IP.
    Try to find something in the OVM documentations and examples.
    It should not be so difficult to make an OVM wrapper around existing verification IP.

    Bests,
    Tiksan

  3. Hi Tiksan,
    In axi master interface you have written “clock alignment” as comment for one sequence.what does it mean .could you please tell about that a little bit more.
    ex:
    sequence sync_posedge; //clock alignment
    @(posedge clk) 1; //if I write 2 here instead of 1 what will happen?
    endsequence

    this sequence has been used in one task called clockalign().

    ex: task clockalign();
    wait(sync_posedge.triggered);
    endtask

    what is the difference between ifc.clockalign() and @ifc.cb . are they same?

Leave a Reply

Your email address will not be published.