The AMBA4 AXI Stream Interface Verification IP (VIP) is a solution for verification the designs with AXI4-Stream interface. The provided verification package includes AXI4-Stream verification IP, Protocol Monitor and integration examples. The VIP is fully compliant with AXI4-Stream specification and can be very powerful tool to check, monitor and debug the AXI4-Stream protocol.
You can download the AXI4-Stream Verification IP from Downloads page.
- Compliant to the AXI4-Stream specification
- Operates as a Master or Slave
- Supports 1, 2, 4, 8, 16 and 32 bytes data block size
- Supports up to 8 user bits per byte
- Supports bus idle insertion between data frames
- Supports full random timings
- Protocol monitor to find bus violations
- Easy integration and usage
- Free SystemVerilog source code
- Download the AXI4-Stream Verification IP and unpack it.
- If you want to run examples
- Go to the following folder: <unpack_dir>/axi4_stream_vip/examples/sim
- For VCS type the following command: vcs -f file_list.f -sverilog
- For QuestaSim10.0c type the following command: qverilog -f file_list.f
- Please read the AXI4-Stream Verification IP User Manual.
If you have any questions please don’t hesitate to contact me.
You can also use article comments below to ask your questions, to report about bugs or to tell some ideas for future improvement. Your comments are always welcome!