Archive for the ‘AMBA Verification IP’ Category
AXI4 Stream Protocol Verification IP
The AMBA4 AXI Stream Interface Verification IP (VIP) is a solution for verification the designs with AXI4-Stream interface. Read the rest of this entry »
AMBA4 AXI-Lite Verification IP
The AMBA4 AXI-Lite Verification IP is an open source solution for verification of AXI-Lite master and slave devices. The provided AXI4-Lite verification package includes master and slave SystemVerilog verification IPs and examples. It will help engineers to quickly create verification environment end test their AXI-Lite master and slave devices. Read the rest of this entry »
AMBA APB Slave Verification IP
This post will only be focused on APB Slave Verification IP (VIP). Master VIP is already discussed in the previous post. Read the rest of this entry »
AMBA APB Master Verification IP
The AMBA Peripheral Bus (APB) Verification IP described here is Verification IP (VIP) written on SystemVerilog for verifying a DUT with AMBA3.0 compliant APB interface.
Loading ...