You can download the AXI4-Lite Verification IP from Downloads page.

Features

1. Free SystemVerilog source code
2. Easy integration and usage
3. Compliant to AMBA4 AXI-Lite Protocol Version: 2.0
4. Operates as a Master or Slave
5. Supports 1, 2, 4, 8 and 16 bytes data block size
6. Supports multiple outstanding transactions
7. Programmable response type
8. On the fly Read/Write response check
9. Supports wait states injection
10. Supports programmable retry and error insertion
11. Supports full random timings
12. Supports misaligned transfers

Limitations

1. Doesn’t support awprot and arprot signals

Installation

1. Download the AXI4-Lite Verification IP and unpack it.
2. If you want to run examples
   1. Go to the following folder: <unpack_dir>/axi4lite_vip/examples/sim
   2. For VCS type the following command: vcs -f file_list.f -sverilog
   3. For QuestaSim6.4 type the following command: qverilog -f file_list.f
3. Please read the AXI4-Lite Verification IP User Manual.

Support

If you have any questions please don’t hesitate to contact me.

You can also use article comments below to ask your questions, to report about bugs or to tell some ideas for future improvement. Your comments are always welcome!

You can download the APB Verification IP if you are registered and logged in.

Features

1. Easy to use.
2. Configurable APB data size.
3. Misaligned transfers.
4. FIFO mode.
5. Fixed and random pready timing delays.
6. Slave error insertion for specified addresses.
7. Failed transaction buffer.

Installation

This Verification IP was tested on VCS2008 and QuestaSim6.4. There is no guarantee that this VIP will work on lower versions.

Download apb_vip.zip and unpack it. Now you are ready to run example. For running Slave example:

1. Go to the following folder: <unpack_dir>/apb_vip/examples/slave/sim
2. If you have VCS type the following command: vcs -f file_list.f -sverilog
3. If you have QuestaSim6.4 type the following command: qverilog -f file_list.f

The test will run for a while. At the end of the test you must have no any unexpected errors reported.

Integration

1. Instantiate apb_s_if interface module to your testbench top file.
2. Import APB_S package to your test.

Interface module is located  in the <unpack_dir>/apb_vip/verification_ip/slave/apb_m_if.sv file.

APB_S package is located in the <unpack_dir>/apb_vip/verification_ip/slave/apb_m.sv file.

This is all you need for integration. Now you can start to use the VIP.

Usage

Before starting to use any commands you need to create ABP_s_env class object. During this object creation you should provide interface module instance name and APB bus data size. After this you can do the following steps:

1. Start APB Master Verification Environment: call startEnv() command.
2. Configure VIP.
3. Start data processing.
4. Print all failed transactions if there are any.

Test Environment

Figure below shows the SystemVerilog test environment where the APB Slave VIP was tested.

As you can see on the figure there is no any DUT in the testsbench. The DUT is modeled inside the test. For connection to the Slave interface the APB Master Verification IP was used. If you already have fully functional and verified master VIP it is better to use it instead of DUT for testing slave VIP. This way is more flexible and you will cover a lot of corner cases.

Support

If you have any questions please don’t hesitate to contact me directly or use article comments below. Your comments are welcome!

If you are registered and logged in you can download the APB Verification IP from here.

The APB VIP package includes Master, Slave verification IPs, user manual and examples. For detailed information about this VIP please read apb_vip_user_manual.pdf. This post will only be focused on APB master VIP. Slave will be discussed in the next post.

The APB Master Verification IP doesn’t support multiple slaves. For testing multiple APB slave devices the external multiplexor should be used.

Features

1. Easy to use.
2. Configurable APB data size.
3. Data word transfer.
4. Data buffer transfer.
5. Misaligned transfers.
6. Configurable valid pready detection.
7. Fixed timing delays.
8. Random timing delays.
9. Slave error detection.
10. Error buffer to hold all failed transactions, Slave errors and time outs.
    
    

Installation

This Verification IP was tested on VCS2008 and QuestaSim6.4. There is no guarantee that this VIP will work on lower versions.

Download apb_vip.zip and unpack it. Now you are ready to run examples.
For running Master example:

1. Go to the following folder: <unpack_dir>/apb_vip/examples/master/sim
2. If you have VCS type the following command: vcs -f file_list.f -sverilog
3. If you have QuestaSim6.4 type the following command: qverilog -f file_list.f

Test is not short and will take about 20 minutes on VCS and about 30 minutes on QuestaSim. At the end of the test you must have no any unexpected errors reported.

Integration

1. Instantiate apb_m_if interface module to your testbench top file.
2. Import APB_M package to your test.

Interface module is located  in the <unpack_dir>/apb_vip/verification_ip/master/apb_m_if.sv file.

APB_M package is located in the <unpack_dir>/apb_vip/verification_ip/master/apb_m.sv file.

This is all you need to do for integration. Now you can start to use the VIP.

Usage

Before starting to use any commands you need to create ABP_m_env class object. During this object creation you should provide interface module instance name and APB bus data size. After this you can do the following steps:

1. Start APB Master Verification Environment: call startEnv() command.
2. Configure VIP.
3. Start data transfers.
4. Print all failed transactions if there are any.

Support

If you have any questions please don’t hesitate to contact me.

You can also use article comments below to ask your questions, to report about bugs or to tell some ideas for future improvement. Your comments are always welcome!