SysWip » SystemVerilog Verification IP http://syswip.com Alternative Verification Mon, 02 Apr 2012 11:17:41 +0000 en hourly 1 http://wordpress.org/?v=3.3.1 Avalon-MM Interface Verification IP http://syswip.com/avalon-mm-interface-verification-ip http://syswip.com/avalon-mm-interface-verification-ip#comments Sun, 25 Mar 2012 18:59:45 +0000 Tiksan http://syswip.com/?p=577 The Altera Avalon-MM Interface Verification IP (VIP) is a solution for verification the designs with Avalon-MM (Memory-Mapped) interface. The provided verification package includes master and slave verification IPs and integration examples. The VIP is fully compliant with protocol specification and can be very powerful tool to check, monitor and debug the Avalon MM protocol.

You can download the Avalon-MM Verification IP from Downloads page.

Features

  1. Compliant to the Avalon Interface specification
  2. Operates as a Master or Slave
  3. Supports 1, 2, 4, 8, 16, 32, 64 and 128 bytes data block size
  4. Supports bus idle insertion between data frames
  5. Supports burst read and write
  6. Supports misaligned transfers
  7. Supports wait request and read data available
  8. Supports full random timings
  9. Easy integration and usage
  10. Free SystemVerilog source code

Limitations

  1. Doesn’t support lock, debugaccess and begintransfer signals

Installation

  1. Download the Avalon-MM Verification IP and unpack it.
  2. If you want to run examples
    1. Go to the following folder: <unpack_dir>/avalon_mm_vip/examples/sim
    2. For VCS type the following command: vcs -f file_list.f -sverilog
    3. For QuestaSim10.0c type the following command: qverilog -f file_list.f
  3. Please read the Avalon-MM Verification IP User Manual.

Support

If you have any questions please don’t hesitate to contact me.

You can also use article comments below to ask your questions, to report about bugs or to tell some ideas for future improvement. Your comments are always welcome!

]]> http://syswip.com/avalon-mm-interface-verification-ip/feed 0 AXI4 Stream Protocol Verification IP http://syswip.com/axi4-stream-protocol-verification-ip-2 http://syswip.com/axi4-stream-protocol-verification-ip-2#comments Mon, 19 Mar 2012 21:35:27 +0000 Tiksan http://syswip.com/?p=572 The AMBA4 AXI Stream Interface Verification IP (VIP) is a solution for verification the designs with AXI4-Stream interface. The provided verification package includes AXI4-Stream verification IP, Protocol Monitor and integration examples. The VIP is fully compliant with AXI4-Stream specification and can be very powerful tool to check, monitor and debug the AXI4-Stream protocol.

You can download the AXI4-Stream Verification IP from Downloads page.

Features

  1. Compliant to the AXI4-Stream specification
  2. Operates as a Master or Slave
  3. Supports 1, 2, 4, 8, 16 and 32 bytes data block size
  4. Supports up to 8 user bits per byte
  5. Supports bus idle insertion between data frames
  6. Supports full random timings
  7. Protocol monitor to find bus violations
  8. Easy integration and usage
  9. Free SystemVerilog source code

Installation

  1. Download the AXI4-Stream Verification IP and unpack it.
  2. If you want to run examples
    1. Go to the following folder: <unpack_dir>/axi4_stream_vip/examples/sim
    2. For VCS type the following command: vcs -f file_list.f -sverilog
    3. For QuestaSim10.0c type the following command: qverilog -f file_list.f
  3. Please read the AXI4-Stream Verification IP User Manual.

Support

If you have any questions please don’t hesitate to contact me.

You can also use article comments below to ask your questions, to report about bugs or to tell some ideas for future improvement. Your comments are always welcome!

]]> http://syswip.com/axi4-stream-protocol-verification-ip-2/feed 0 CAN Verification IP http://syswip.com/can-verification-ip http://syswip.com/can-verification-ip#comments Fri, 27 May 2011 11:28:27 +0000 Tiksan http://syswip.com/?p=548 The CAN(Controller area network) Bus Verification IP (VIP) is a solution for verification of CAN2.0 designs. The provided verification package includes CAN2.0 verification IP, integration examples and extensive test suit which covers most of the scenarios defined in the ISO/DIS 16845(Conformance test plan). The VIP is fully compliant with CAN2.0B specification and can be very powerful tool to check, monitor and debug the CAN2.0-Bus protocol.

You can download the CAN2.0-Bus Verification IP from Downloads page.

Features

  1. Compliant to the CAN2.0B specification
  2. Supports all frame types: Data frames, Remote frames, Error frames Overload frames
  3. Automatic response to the remote frames
  4. Supports all error types: Bit errors, Stuff errors, CRC errors, Form errors, Acknowledgment error
  5. Automatic re-transmission of the corrupted data or remote frames
  6. Programmable TX and RX error counters
  7. Supports all types of error injection
  8. Supports programmable bus idle insertion between data frames
  9. Supports data or remote frame transmission at the 3rd intermission bit
  10. Automatic overload frame transmission after data or remote frames
  11. Separate RX data buffers for each identifiers
  12. Suports full debug frame transmission to test all posible corner cases
  13. Extensive status report
  14. Full duplex
  15. Easy integration and usage
  16. Free SystemVerilog source code

Installation

  1. Download the CAN2.0 Verification IP and unpack it.
  2. If you want to run examples
    1. Go to the following folder: <unpack_dir>/can_vip/examples/sim
    2. For VCS type the following command: vcs -f file_list.f -sverilog
    3. For QuestaSim6.4 type the following command: qverilog -f file_list.f
  3. Please read the CAN-Bus Verification IP User Manual.

Support

If you have any questions please don’t hesitate to contact me.

You can also use article comments below to ask your questions, to report about bugs or to tell some ideas for future improvement. Your comments are always welcome!

]]> http://syswip.com/can-verification-ip/feed 0 MDIO Verification IP http://syswip.com/mdio-verification-ip http://syswip.com/mdio-verification-ip#comments Sun, 01 Aug 2010 08:06:30 +0000 Tiksan http://syswip.com/?p=541 The MDIO (Management Data Input/Output) is a serial bus structure defined for the Ethernet protocol. MDIO is defined to connect Media Access Control (MAC) devices with PHY devices, providing a standardized access method to internal registers of PHY devices.
The MDIO Verification IP is an open source solution for verification of MDIO master (STA, station management entity) and slave (MMD, MDIO Manageable Device) devices. The provided MDIO verification package includes master and slave SystemVerilog verification IPs and examples. It will help engineers to quickly create verification environment end test their MDIO master and slave devices.

You can download the MDIO Verification IP from Downloads page.

Features

  1. Free SystemVerilog source code
  2. Easy integration and usage
  3. Compliant to the MDIO protocol specified by the IEEE 802.3 standard “Clause 22″
  4. Supports extended operation mode defined in the 802.3ae standard “Clause 45″
  5. Supports multiple slaves
  6. Supports wait states injection
  7. Supports full random timings

Installation

  1. Download the MDIO Verification IP and unpack it.
  2. If you want to run examples
    1. Go to the following folder: <unpack_dir>/mdio_vip/examples/sim
    2. For VCS type the following command: vcs -f file_list.f -sverilog
    3. For QuestaSim6.4 type the following command: qverilog -f file_list.f
  3. Please read the MDIO Verification IP User Manual.

Support

If you have any questions please don’t hesitate to contact me.

You can also use article comments below to ask your questions, to report about bugs or to tell some ideas for future improvement. Your comments are always welcome!

]]> http://syswip.com/mdio-verification-ip/feed 0 AMBA4 AXI-Lite Verification IP http://syswip.com/axi4-lite-verification-ip http://syswip.com/axi4-lite-verification-ip#comments Fri, 04 Jun 2010 10:04:58 +0000 Tiksan http://syswip.com/?p=528 The AMBA4 AXI-Lite Verification IP is an open source solution for verification of AXI-Lite master and slave devices. The provided AXI4-Lite verification package includes master and slave SystemVerilog verification IPs and examples. It will help engineers to quickly create verification environment end test their AXI-Lite master and slave devices.

You can download the AXI4-Lite Verification IP from Downloads page.

Features

  1. Free SystemVerilog source code
  2. Easy integration and usage
  3. Compliant to AMBA4 AXI-Lite Protocol Version: 2.0
  4. Operates as a Master or Slave
  5. Supports 1, 2, 4, 8 and 16 bytes data block size
  6. Supports multiple outstanding transactions
  7. Programmable response type
  8. On the fly Read/Write response check
  9. Supports wait states injection
  10. Supports programmable retry and error insertion
  11. Supports full random timings
  12. Supports misaligned transfers

Limitations

  1. Doesn’t support awprot and arprot signals

Installation

  1. Download the AXI4-Lite Verification IP and unpack it.
  2. If you want to run examples
    1. Go to the following folder: <unpack_dir>/axi4lite_vip/examples/sim
    2. For VCS type the following command: vcs -f file_list.f -sverilog
    3. For QuestaSim type the following command: qverilog -f file_list.f
  3. Please read the AXI4-Lite Verification IP User Manual.

Support

If you have any questions please don’t hesitate to contact me.

You can also use article comments below to ask your questions, to report about bugs or to tell some ideas for future improvement. Your comments are always welcome!

]]> http://syswip.com/axi4-lite-verification-ip/feed 0 Avalon-ST Streaming Interface Verification IP http://syswip.com/avalonst-verification-ip http://syswip.com/avalonst-verification-ip#comments Fri, 09 Apr 2010 14:30:30 +0000 Tiksan http://syswip.com/?p=522 The Avalon-ST Verification IP is a simple solution for verification of Altera Avalon Streaming source and sink interfaces. The provided Avalon-ST verification package includes master (source) and slave (sink) SystemVerilog verification IPs and examples. It will help engineers to quickly create verification environment end test their Avalon Streaming interfaces.

You can download the Avalon-ST Verification IP from Downloads page.

Features

  1. Free SystemVerilog source code
  2. Easy integration and usage
  3. Compliant to Avalon Interface Specifications Ver1.2
  4. Operates as a Master or Slave
  5. Supports 1, 2, 4, 8, 16 and 32 bytes data block size
  6. Configurable endians (little endian or big endian)
  7. Supports wait states injection
  8. Supports full random “empty” value generation
  9. Supports full random timings
  10. Supports wrong start/end of packet insertion and detection

Limitations

  1. Doesn’t support multiple channels
  2. Doesn’t support error signals
  3. readyLatency is fixed to zero

Installation

  1. Download Avalon-ST Verification IP and unpack it.
  2. If you want to run examples
    1. Go to the following folder: <unpack_dir>/avalonst_vip/examples/sim
    2. For VCS type the following command: vcs -f file_list.f -sverilog
    3. For QuestaSim6.4 type the following command: qverilog -f file_list.f
  3. Please read the Avalon-ST Verification IP User Manual.

Support

If you have any questions please don’t hesitate to contact me.

You can also use article comments below to ask your questions, to report about bugs or to tell some ideas for future improvement. Your comments are always welcome!

]]> http://syswip.com/avalonst-verification-ip/feed 1 Wishbone Verification IP http://syswip.com/wishbone-verification-ip http://syswip.com/wishbone-verification-ip#comments Fri, 05 Feb 2010 16:04:35 +0000 Tiksan http://syswip.com/?p=495 The Wishbone Verification IP is a simple solution for verification of Wishbone B3 master and slave devices. The provided Wishbone verification package includes master and slave SystemVerilog verification IPs and examples. It will help engineers to quickly create verification environment end test their Wishbone master and slave devices.

You can download the Wishbone Verification IP from Downloads page.

Features

  1. Free SystemVerilog source code
  2. Easy integration and usage
  3. Compliant to Wishbone B3 Protocol
  4. Operates as a Master or Slave
  5. Supports 1, 2, 4 and 8 bytes data block size
  6. Supports single cycle transfers
  7. Supports wait states injection
  8. Supports programmable retry and error insertion
  9. Supports full random timings
  10. Supports misaligned transfers

Limitations

  1. Doesn’t support TAGs
  2. Doesn’t support Lock signal

Installation

  1. Download Wishbone Verification IP and unpack it.
  2. If you want to run examples
    1. Go to the following folder: <unpack_dir>/wishbone_vip/examples/sim
    2. For VCS type the following command: vcs -f file_list.f -sverilog
    3. For QuestaSim6.4 type the following command: qverilog -f file_list.f
  3. Please read the Wishbone Verification IP User Manual.

Support

If you have any questions please don’t hesitate to contact me.

You can also use article comments below to ask your questions, to report about bugs or to tell some ideas for future improvement. Your comments are always welcome!

]]> http://syswip.com/wishbone-verification-ip/feed 4 SPI Verification IP http://syswip.com/spi-verification-ip http://syswip.com/spi-verification-ip#comments Wed, 16 Dec 2009 22:42:49 +0000 Tiksan http://syswip.com/?p=449 The SPI Verification IP is a simple solution for verification of SPI master and slave devices. The provided SPI verification package includes master and slave SystemVerilog verification IPs and examples. It will help engineers to quickly create verification environment end test their SPI master and slave devices. 

You can download the SPI Verification IP from Downloads page.

Features

  1. Free SystemVerilog source code
  2. Easy integration and usage
  3. Supports SPI bus specification as defined in M68HC11 user manual rev 5.0
  4. Operates as a Master or Slave
  5. Supports multiple slaves
  6. Supports clock polarity selections
  7. Supports CPHA selection
  8. Supports both MSB and LSB data transmissions
  9. Fully configurable and accurate bus timing
  10. Supports single and burst transfers
  11. Supports different burst sizes
  12. Supports wait states injection

Installation

  1. Download SPI Verification IP and unpack it.
  2. If you want to run examples
    1. Go to the following folder: <unpack_dir>/spi_vip/examples/sim
    2. For VCS type the following command: vcs -f file_list.f -sverilog
    3. For QuestaSim6.4 type the following command: qverilog -f file_list.f
  3. Please read the SPI Serial Peripheral Interface Verification IP User Manual.

Support

If you have any questions please don’t hesitate to contact me.

You can also use article comments below to ask your questions, to report about bugs or to tell some ideas for future improvement. Your comments are always welcome!

]]> http://syswip.com/spi-verification-ip/feed 5 I2C Verification IP http://syswip.com/i2c-verification-ip http://syswip.com/i2c-verification-ip#comments Tue, 08 Dec 2009 09:30:08 +0000 Tiksan http://syswip.com/?p=419 The I2C Verification IP is a solution for verification of I2C master and slave devices. The provided I2C verification package includes master and slave verification IPs and examples. It will help engineers to quickly create verification environment end test their I2C master and slave devices.

You can download the I2C Verification IP from Downloads page.

Features

  1. Free SystemVerilog source code
  2. Easy integration and usage
  3. Supports I2C bus specification Rev. 03 – 19 June 2007
  4. Supports standard, fast, and fast plus speed modes
  5. Operates as a Master or Slave
  6. Supports multiple slaves
  7. Supports 7 and 10 bit addressing
  8. Fully custom and accurate bus timing
  9. Random delay insertion
  10. Detects not acknowledge errors

Limitations

  1. Does not support Multi-master
  2. Does not support Clock stretching
  3. Does not support General Call address

Installation

  1. Download I2C Verification IP and unpack it.
  2. If you want to run examples
    1. Go to the following folder: <unpack_dir>/i2c_vip/examples/sim
    2. For VCS type the following command: vcs -f file_list.f -sverilog
    3. For QuestaSim6.4 type the following command: qverilog -f file_list.f
  3. Please read the I2C Serial Bus Verification IP User Manual.

Support

If you have any questions please don’t hesitate to contact me.

You can also use article comments below to ask your questions, to report about bugs or to tell some ideas for future improvement. Your comments are always welcome!

]]> http://syswip.com/i2c-verification-ip/feed 29 AMBA APB Slave Verification IP http://syswip.com/amba-apb-slave-verification-ip http://syswip.com/amba-apb-slave-verification-ip#comments Fri, 30 Oct 2009 12:02:15 +0000 Tiksan http://syswip.com/wp/?p=235 This post will only be focused on APB Slave Verification IP (VIP). Master VIP is already discussed in the previous post.

Features

  1. Easy to use.
  2. Configurable APB data size.
  3. Misaligned transfers.
  4. FIFO mode.
  5. Fixed and random pready timing delays.
  6. Slave error insertion for specified addresses.
  7. Failed transaction buffer.

Installation

This Verification IP was tested on VCS2008 and QuestaSim6.4. There is no guarantee that this VIP will work on lower versions.

Download apb_vip.zip and unpack it. Now you are ready to run example. For running Slave example:

  1. Go to the following folder: <unpack_dir>/apb_vip/examples/slave/sim
  2. If you have VCS type the following command: vcs -f file_list.f -sverilog
  3. If you have QuestaSim6.4 type the following command: qverilog -f file_list.f

The test will run for a while. At the end of the test you must have no any unexpected errors reported.

Integration

  1. Instantiate apb_s_if interface module to your testbench top file.
  2. Import APB_S package to your test.

Interface module is located  in the <unpack_dir>/apb_vip/verification_ip/slave/apb_m_if.sv file.

APB_S package is located in the <unpack_dir>/apb_vip/verification_ip/slave/apb_m.sv file.

This is all you need for integration. Now you can start to use the VIP.

Usage

Before starting to use any commands you need to create ABP_s_env class object. During this object creation you should provide interface module instance name and APB bus data size. After this you can do the following steps:

  1. Start APB Master Verification Environment: call startEnv() command.
  2. Configure VIP.
  3. Start data processing.
  4. Print all failed transactions if there are any.

Test Environment

Figure below shows the SystemVerilog test environment where the APB Slave VIP was tested.

SystemVerilog testbench for APB slave devices

As you can see on the figure there is no any DUT in the testsbench. The DUT is modeled inside the test. For connection to the Slave interface the APB Master Verification IP was used. If you already have fully functional and verified master VIP it is better to use it instead of DUT for testing slave VIP. This way is more flexible and you will cover a lot of corner cases.

Support

If you have any questions please don’t hesitate to contact me directly or use article comments below. Your comments are welcome!

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