You can download the MDIO Verification IP from Downloads page.

Features

1. Free SystemVerilog source code
2. Easy integration and usage
3. Compliant to the MDIO protocol specified by the IEEE 802.3 standard “Clause 22″
4. Supports extended operation mode defined in the 802.3ae standard “Clause 45″
5. Supports multiple slaves
6. Supports wait states injection
7. Supports full random timings

Installation

1. Download the MDIO Verification IP and unpack it.
2. If you want to run examples
   1. Go to the following folder: <unpack_dir>/mdio_vip/examples/sim
   2. For VCS type the following command: vcs -f file_list.f -sverilog
   3. For QuestaSim6.4 type the following command: qverilog -f file_list.f
3. Please read the MDIO Verification IP User Manual.

Support

If you have any questions please don’t hesitate to contact me.

You can also use article comments below to ask your questions, to report about bugs or to tell some ideas for future improvement. Your comments are always welcome!

You can download the AXI4-Lite Verification IP from Downloads page.

Features

1. Free SystemVerilog source code
2. Easy integration and usage
3. Compliant to AMBA4 AXI-Lite Protocol Version: 2.0
4. Operates as a Master or Slave
5. Supports 1, 2, 4, 8 and 16 bytes data block size
6. Supports multiple outstanding transactions
7. Programmable response type
8. On the fly Read/Write response check
9. Supports wait states injection
10. Supports programmable retry and error insertion
11. Supports full random timings
12. Supports misaligned transfers

Limitations

1. Doesn’t support awprot and arprot signals

Installation

1. Download the AXI4-Lite Verification IP and unpack it.
2. If you want to run examples
   1. Go to the following folder: <unpack_dir>/axi4lite_vip/examples/sim
   2. For VCS type the following command: vcs -f file_list.f -sverilog
   3. For QuestaSim6.4 type the following command: qverilog -f file_list.f
3. Please read the AXI4-Lite Verification IP User Manual.

Support

If you have any questions please don’t hesitate to contact me.

You can also use article comments below to ask your questions, to report about bugs or to tell some ideas for future improvement. Your comments are always welcome!

You can download the Avalon-ST Verification IP from Downloads page.

Features

1. Free SystemVerilog source code
2. Easy integration and usage
3. Compliant to Avalon Interface Specifications Ver1.2
4. Operates as a Master or Slave
5. Supports 1, 2, 4, 8, 16 and 32 bytes data block size
6. Configurable endians (little endian or big endian)
7. Supports wait states injection
8. Supports full random “empty” value generation
9. Supports full random timings
10. Supports wrong start/end of packet insertion and detection

Limitations

1. Doesn’t support multiple channels
2. Doesn’t support error signals
3. readyLatency is fixed to zero

Installation

1. Download Avalon-ST Verification IP and unpack it.
2. If you want to run examples
   1. Go to the following folder: <unpack_dir>/avalonst_vip/examples/sim
   2. For VCS type the following command: vcs -f file_list.f -sverilog
   3. For QuestaSim6.4 type the following command: qverilog -f file_list.f
3. Please read the Avalon-ST Verification IP User Manual.

Support

If you have any questions please don’t hesitate to contact me.

You can also use article comments below to ask your questions, to report about bugs or to tell some ideas for future improvement. Your comments are always welcome!

You can download the Wishbone Verification IP from Downloads page.

Features

1. Free SystemVerilog source code
2. Easy integration and usage
3. Compliant to Wishbone B3 Protocol
4. Operates as a Master or Slave
5. Supports 1, 2, 4 and 8 bytes data block size
6. Supports single cycle transfers
7. Supports wait states injection
8. Supports programmable retry and error insertion
9. Supports full random timings
10. Supports misaligned transfers

Limitations

1. Doesn’t support TAGs
2. Doesn’t support Lock signal

Installation

1. Download Wishbone Verification IP and unpack it.
2. If you want to run examples
   1. Go to the following folder: <unpack_dir>/wishbone_vip/examples/sim
   2. For VCS type the following command: vcs -f file_list.f -sverilog
   3. For QuestaSim6.4 type the following command: qverilog -f file_list.f
3. Please read the Wishbone Verification IP User Manual.

Support

If you have any questions please don’t hesitate to contact me.

You can also use article comments below to ask your questions, to report about bugs or to tell some ideas for future improvement. Your comments are always welcome!

You can download the SPI Verification IP from Downloads page.

Features

1. Free SystemVerilog source code
2. Easy integration and usage
3. Supports SPI bus specification as defined in M68HC11 user manual rev 5.0
4. Operates as a Master or Slave
5. Supports multiple slaves
6. Supports clock polarity selections
7. Supports CPHA selection
8. Supports both MSB and LSB data transmissions
9. Fully configurable and accurate bus timing
10. Supports single and burst transfers
11. Supports different burst sizes
12. Supports wait states injection

Installation

1. Download SPI Verification IP and unpack it.
2. If you want to run examples
   1. Go to the following folder: <unpack_dir>/spi_vip/examples/sim
   2. For VCS type the following command: vcs -f file_list.f -sverilog
   3. For QuestaSim6.4 type the following command: qverilog -f file_list.f
3. Please read the SPI Serial Peripheral Interface Verification IP User Manual.

Support

If you have any questions please don’t hesitate to contact me.

You can also use article comments below to ask your questions, to report about bugs or to tell some ideas for future improvement. Your comments are always welcome!

You can download the I2C Verification IP from Downloads page.

Features

1. Free SystemVerilog source code
2. Easy integration and usage
3. Supports I2C bus specification Rev. 03 – 19 June 2007
4. Supports standard, fast, and fast plus speed modes
5. Operates as a Master or Slave
6. Supports multiple slaves
7. Supports 7 and 10 bit addressing
8. Fully custom and accurate bus timing
9. Random delay insertion
10. Detects not acknowledge errors

Limitations

1. Does not support Multi-master
2. Does not support Clock stretching
3. Does not support General Call address

Installation

1. Download I2C Verification IP and unpack it.
2. If you want to run examples
   1. Go to the following folder: <unpack_dir>/i2c_vip/examples/sim
   2. For VCS type the following command: vcs -f file_list.f -sverilog
   3. For QuestaSim6.4 type the following command: qverilog -f file_list.f
3. Please read the I2C Serial Bus Verification IP User Manual.

Support

If you have any questions please don’t hesitate to contact me.

You can also use article comments below to ask your questions, to report about bugs or to tell some ideas for future improvement. Your comments are always welcome!

You can download the APB Verification IP if you are registered and logged in.

Features

1. Easy to use.
2. Configurable APB data size.
3. Misaligned transfers.
4. FIFO mode.
5. Fixed and random pready timing delays.
6. Slave error insertion for specified addresses.
7. Failed transaction buffer.

Installation

This Verification IP was tested on VCS2008 and QuestaSim6.4. There is no guarantee that this VIP will work on lower versions.

Download apb_vip.zip and unpack it. Now you are ready to run example. For running Slave example:

1. Go to the following folder: <unpack_dir>/apb_vip/examples/slave/sim
2. If you have VCS type the following command: vcs -f file_list.f -sverilog
3. If you have QuestaSim6.4 type the following command: qverilog -f file_list.f

The test will run for a while. At the end of the test you must have no any unexpected errors reported.

Integration

1. Instantiate apb_s_if interface module to your testbench top file.
2. Import APB_S package to your test.

Interface module is located  in the <unpack_dir>/apb_vip/verification_ip/slave/apb_m_if.sv file.

APB_S package is located in the <unpack_dir>/apb_vip/verification_ip/slave/apb_m.sv file.

This is all you need for integration. Now you can start to use the VIP.

Usage

Before starting to use any commands you need to create ABP_s_env class object. During this object creation you should provide interface module instance name and APB bus data size. After this you can do the following steps:

1. Start APB Master Verification Environment: call startEnv() command.
2. Configure VIP.
3. Start data processing.
4. Print all failed transactions if there are any.

Test Environment

Figure below shows the SystemVerilog test environment where the APB Slave VIP was tested.

As you can see on the figure there is no any DUT in the testsbench. The DUT is modeled inside the test. For connection to the Slave interface the APB Master Verification IP was used. If you already have fully functional and verified master VIP it is better to use it instead of DUT for testing slave VIP. This way is more flexible and you will cover a lot of corner cases.

Support

If you have any questions please don’t hesitate to contact me directly or use article comments below. Your comments are welcome!

If you are registered and logged in you can download the APB Verification IP from here.

The APB VIP package includes Master, Slave verification IPs, user manual and examples. For detailed information about this VIP please read apb_vip_user_manual.pdf. This post will only be focused on APB master VIP. Slave will be discussed in the next post.

The APB Master Verification IP doesn’t support multiple slaves. For testing multiple APB slave devices the external multiplexor should be used.

Features

1. Easy to use.
2. Configurable APB data size.
3. Data word transfer.
4. Data buffer transfer.
5. Misaligned transfers.
6. Configurable valid pready detection.
7. Fixed timing delays.
8. Random timing delays.
9. Slave error detection.
10. Error buffer to hold all failed transactions, Slave errors and time outs.
    
    

Installation

This Verification IP was tested on VCS2008 and QuestaSim6.4. There is no guarantee that this VIP will work on lower versions.

Download apb_vip.zip and unpack it. Now you are ready to run examples.
For running Master example:

1. Go to the following folder: <unpack_dir>/apb_vip/examples/master/sim
2. If you have VCS type the following command: vcs -f file_list.f -sverilog
3. If you have QuestaSim6.4 type the following command: qverilog -f file_list.f

Test is not short and will take about 20 minutes on VCS and about 30 minutes on QuestaSim. At the end of the test you must have no any unexpected errors reported.

Integration

1. Instantiate apb_m_if interface module to your testbench top file.
2. Import APB_M package to your test.

Interface module is located  in the <unpack_dir>/apb_vip/verification_ip/master/apb_m_if.sv file.

APB_M package is located in the <unpack_dir>/apb_vip/verification_ip/master/apb_m.sv file.

This is all you need to do for integration. Now you can start to use the VIP.

Usage

Before starting to use any commands you need to create ABP_m_env class object. During this object creation you should provide interface module instance name and APB bus data size. After this you can do the following steps:

1. Start APB Master Verification Environment: call startEnv() command.
2. Configure VIP.
3. Start data transfers.
4. Print all failed transactions if there are any.

Support

If you have any questions please don’t hesitate to contact me.

You can also use article comments below to ask your questions, to report about bugs or to tell some ideas for future improvement. Your comments are always welcome!

So let me start.

Each time I have a new verification project the first question I always ask is which interfaces DUT (Device Under Test) has. Depending on the answer my testbench creation time can be very different, from several days if I already have verification IP up to several weeks even months. For this simple environment I choose AES Cryptographic Engine as a DUT and the answer for my first question is AMBA APB Slave interface. So I need AMBA APB Master Verification IP as a starting point.

Another important question is if I have a model for DUT. This will decrease environment design time a lot. So here I will use System Verilog behavioral model for AES algorithm.

Let’s see the simple verification environment block diagram in the figure below and discuss each block.

AES Cryptographic Engine is a synthesizable verilog RTL with APB slave interface which should be instantiated in the testbench top file.

I don’t want to discuss more complex clock and reset generation module in this post. The simplest clock and reset generation will be used. But one of the future posts will focus on very useful clock and reset generation module.

APB Master VIP is a collection of SystemVerilog classes which should be connected to the DUT via SystemVerilog interfaces. Test module will communicate with DUT only using APB Master VIP functions.

AES model is a SystemVerilog class with corresponding methods. Test module should call these methods to have a valid data which can be compared with the data from the DUT.

Test module is a SystemVerilog program block where all tests are executed.

Now let me describe what the basic test should do.

The first thing is environment initialization. After initialization the test will generate input data and send it to DUT via VIP. The same data should be sent to the model and get expected data from it. After this the test should read output data from DUT and compare it with the expected one. At the end detailed report is generated to make future debugging easy.
The above mentioned steps should be repeated until 100% coverage is achieved.

In this introductory post I would like to explain what my blog is about. As you can see from about page the main reason I started this blog is the absence of free Verification IPs in the web. So the main part of this blog will be focused on SystemVerilog Verification IPs.

Functional models are also very important part in the verification process. And good functional models will accelerate your verification a lot. So they will definitely find a place in my blog.

In future if I have any good ideas which will make your verification easy I will share them with you.

Each product will be available for registered users from the download page.

Please remember your feedback is very important for me. Don’t hesitate to leave your comments. It will help me to improve my products to satisfy your needs.

Help me to help you.

I’m doing my best to make your verification easy.

Verification must be easy!