The I2C Verification IP is a solution for verification of I2C master and slave devices. The provided I2C verification package includes master and slave verification IPs and examples. It will help engineers to quickly create verification environment end test their I2C master and slave devices.
You can download the I2C Verification IP from Downloads page.
- Free SystemVerilog source code
- Easy integration and usage
- Supports I2C bus specification Rev. 03 – 19 June 2007
- Supports standard, fast, and fast plus speed modes
- Operates as a Master or Slave
- Supports multiple slaves
- Supports 7 and 10 bit addressing
- Fully custom and accurate bus timing
- Random delay insertion
- Detects not acknowledge errors
- Does not support Multi-master
- Does not support Clock stretching
- Does not support General Call address
- Download I2C Verification IP and unpack it.
- If you want to run examples
- Go to the following folder: <unpack_dir>/i2c_vip/examples/sim
- For VCS type the following command: vcs -f file_list.f -sverilog
- For QuestaSim6.4 type the following command: qverilog -f file_list.f
- Please read the I2C Serial Bus Verification IP User Manual.
If you have any questions please don’t hesitate to contact me.
You can also use article comments below to ask your questions, to report about bugs or to tell some ideas for future improvement. Your comments are always welcome!