MDIO Verification IP

The MDIO (Management Data Input/Output) is a serial bus structure defined for the Ethernet protocol. MDIO is defined to connect Media Access Control (MAC) devices with PHY devices, providing a standardized access method to internal registers of PHY devices.
The MDIO Verification IP is an open source solution for verification of MDIO master (STA, station management entity) and slave (MMD, MDIO Manageable Device) devices. The provided MDIO verification package includes master and slave SystemVerilog verification IPs and examples. It will help engineers to quickly create verification environment end test their MDIO master and slave devices.

You can download the MDIO Verification IP from Downloads page.


  1. Free SystemVerilog source code
  2. Easy integration and usage
  3. Compliant to the MDIO protocol specified by the IEEE 802.3 standard “Clause 22”
  4. Supports extended operation mode defined in the 802.3ae standard “Clause 45”
  5. Supports multiple slaves
  6. Supports wait states injection
  7. Supports full random timings


  1. Download the MDIO Verification IP and unpack it.
  2. If you want to run examples
    1. Go to the following folder: <unpack_dir>/mdio_vip/examples/sim
    2. For VCS type the following command: vcs -f file_list.f -sverilog
    3. For QuestaSim6.4 type the following command: qverilog -f file_list.f
  3. Please read the MDIO Verification IP User Manual.


If you have any questions please don’t hesitate to contact me.

You can also use article comments below to ask your questions, to report about bugs or to tell some ideas for future improvement. Your comments are always welcome!

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