Before starting to write any posts about Verification IPs in this introductory I would like to describe a simple SystemVerilog Verification Environment. I’ll provide more details about each module which you find in this simple environment in the future posts. I think this is a good starting point for you to follow my thoughts. And after several posts we will have a fully functional SystemVerilog verification environment.
So let me start.
Each time I have a new verification project the first question I always ask is which interfaces DUT (Device Under Test) has. Depending on the answer my testbench creation time can be very different, from several days if I already have verification IP up to several weeks even months. For this simple environment I choose AES Cryptographic Engine as a DUT and the answer for my first question is AMBA APB Slave interface. So I need AMBA APB Master Verification IP as a starting point.
Another important question is if I have a model for DUT. This will decrease environment design time a lot. So here I will use System Verilog behavioral model for AES algorithm.
Let’s see the simple verification environment block diagram in the figure below and discuss each block.
AES Cryptographic Engine is a synthesizable verilog RTL with APB slave interface which should be instantiated in the testbench top file.
I don’t want to discuss more complex clock and reset generation module in this post. The simplest clock and reset generation will be used. But one of the future posts will focus on very useful clock and reset generation module.
APB Master VIP is a collection of SystemVerilog classes which should be connected to the DUT via SystemVerilog interfaces. Test module will communicate with DUT only using APB Master VIP functions.
AES model is a SystemVerilog class with corresponding methods. Test module should call these methods to have a valid data which can be compared with the data from the DUT.
Test module is a SystemVerilog program block where all tests are executed.
Now let me describe what the basic test should do.
The first thing is environment initialization. After initialization the test will generate input data and send it to DUT via VIP. The same data should be sent to the model and get expected data from it. After this the test should read output data from DUT and compare it with the expected one. At the end detailed report is generated to make future debugging easy.
The above mentioned steps should be repeated until 100% coverage is achieved.