SPI Verification IP

The SPI Verification IP is a simple solution for verification of SPI master and slave devices. The provided SPI verification package includes master and slave SystemVerilog verification IPs and examples. It will help engineers to quickly create verification environment end test their SPI master and slave devices. 

You can download the SPI Verification IP from Downloads page.


  1. Free SystemVerilog source code
  2. Easy integration and usage
  3. Supports SPI bus specification as defined in M68HC11 user manual rev 5.0
  4. Operates as a Master or Slave
  5. Supports multiple slaves
  6. Supports clock polarity selections
  7. Supports CPHA selection
  8. Supports both MSB and LSB data transmissions
  9. Fully configurable and accurate bus timing
  10. Supports single and burst transfers
  11. Supports different burst sizes
  12. Supports wait states injection


  1. Download SPI Verification IP and unpack it.
  2. If you want to run examples
    1. Go to the following folder: <unpack_dir>/spi_vip/examples/sim
    2. For VCS type the following command: vcs -f file_list.f -sverilog
    3. For QuestaSim6.4 type the following command: qverilog -f file_list.f
  3. Please read the SPI Serial Peripheral Interface Verification IP User Manual.


If you have any questions please don’t hesitate to contact me.

You can also use article comments below to ask your questions, to report about bugs or to tell some ideas for future improvement. Your comments are always welcome!

9 thoughts on “SPI Verification IP

  1. Hi Tiksan,
    First of all, thank you for creating such a blog.
    The SPI verification IP data you offer here is great, while the User Manual is well presented and useful.

    I use VHDL and Verilog and am not conversant with SystemVerilog. However, I agree that verification efficiency, quality and reusability is increased with the type of abstraction offered by languages such as SystemVerilog. So I need to get myself trained really.

    In the meantime, I have a spi_slave module written in Verilog, and was wondering whether you could offer some pointers on how I can integrate my Verilog module with your SPI verification IP? The module implementation is close to the hardware (as is usually Verilog or VHDL code) and for instance, it has a system clk input which is not in your spi_slave interface.

    Thanks in advance for any advice.

  2. Hi!

    I try run VIP in cadence IUS8.2 and have next errors:

    irun: *N,CLEAN: Removing existing directory ./INCA_libs.
    dataOutBuff = {dataOutBuff, this.tr.dataByte};
    ncvlog: *E,TYCMPAT (spi_s.sv,242|20): assignment operator type check failed (expecting datatype compatible with ‘queue of bit8’ but found ‘packed array’ instead).
    dataOutBuff = {dataOutBuff, this.tr.dataByte};
    ncvlog: *E,TYPEERR (spi_s.sv,242|31): {} concatenation operator operand type is illegal.

    Best regards,

  3. Hi Tiksan

    What is the reason that you have used two interface files for master and slave. Can’t we use a single interface file and use modports for the master and slave.

  4. Thanks for the files, very helpful!

    Is it possible to get free SPI DUT for testing the code? Can I know when you wrote the codes, which DUT you have used?


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