The SPI Verification IP is a simple solution for verification of SPI master and slave devices. The provided SPI verification package includes master and slave SystemVerilog verification IPs and examples. It will help engineers to quickly create verification environment end test their SPI master and slave devices.
You can download the SPI Verification IP from Downloads page.
- Free SystemVerilog source code
- Easy integration and usage
- Supports SPI bus specification as defined in M68HC11 user manual rev 5.0
- Operates as a Master or Slave
- Supports multiple slaves
- Supports clock polarity selections
- Supports CPHA selection
- Supports both MSB and LSB data transmissions
- Fully configurable and accurate bus timing
- Supports single and burst transfers
- Supports different burst sizes
- Supports wait states injection
- Download SPI Verification IP and unpack it.
- If you want to run examples
- Go to the following folder: <unpack_dir>/spi_vip/examples/sim
- For VCS type the following command: vcs -f file_list.f -sverilog
- For QuestaSim6.4 type the following command: qverilog -f file_list.f
- Please read the SPI Serial Peripheral Interface Verification IP User Manual.
If you have any questions please don’t hesitate to contact me.
You can also use article comments below to ask your questions, to report about bugs or to tell some ideas for future improvement. Your comments are always welcome!