Welcome
Welcome to my blog!
In this introductory post I would like to explain what my blog is about. As you can see from about page the main reason I started this blog is the absence of free Verification IPs in the web. So the main part of this blog will be focused on SystemVerilog Verification IPs.
Functional models are also very important part in the verification process. And good functional models will accelerate your verification a lot. So they will definitely find a place in my blog.
In future if I have any good ideas which will make your verification easy I will share them with you.
Each product will be available for registered users from the download page.
Please remember your feedback is very important for me. Don’t hesitate to leave your comments. It will help me to improve my products to satisfy your needs.
Help me to help you.
I’m doing my best to make your verification easy.
Verification must be easy!
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Seems to be useful. Good luck.
firstly thank you for your blogs. its very useful for me. because i am newbie at sv. and what do you suggest me? wher i am starting?
Hi zula,
You can start with the following book:
“SystemVerilog for Verification, by Chris Spear,
Second Edition”.
Then you can read the following book:
“Writing Testbenches using SystemVerilog,
by Janick Bergeron
Synopsys, Inc.”
This will be very good start for you.
Best Regards,
Tiksan.
Very nice blog. Thanks for sharing.