Welcome

Welcome to my blog!

In this introductory post I would like to explain what my blog is about. As you can see from about page the main reason I started this blog is the absence of free Verification IPs in the web. So the main part of this blog will be focused on SystemVerilog Verification IPs.

Functional models are also very important part in the verification process. And good functional models will accelerate your verification a lot. So they will definitely find a place in my blog.

In future if I have any good ideas which will make your verification easy I will share them with you.

Please remember your feedback is very important for me. Don’t hesitate to leave your comments. It will help me to improve my designs to satisfy your needs.

Help me to help you.

I’m doing my best to make your verification easy.

Verification must be easy!

17 thoughts on “Welcome

  1. firstly thank you for your blogs. its very useful for me. because i am newbie at sv. and what do you suggest me? wher i am starting?

  2. Hi zula,

    You can start with the following book:

    “SystemVerilog for Verification, by Chris Spear,
    Second Edition”.

    Then you can read the following book:

    “Writing Testbenches using SystemVerilog,
    by Janick Bergeron
    Synopsys, Inc.”

    This will be very good start for you.

    Best Regards,
    Tiksan.

  3. Can you share some interview question and tips on verification, that is expected from 1-2 year experience candidate.It will be a great help.
    ash

  4. Hi,

    This site is really good. I was looking to write VIPs and they’re already here. I need to know how to write VIPs that can be translated into any language.. eg verilog, SystemC, SystemVerilog. How do I get started writing VIPs?

    Can we implement queues, command FIFOs and FIFO interfaces in Verilog like the ones in SystemC?? SysC has TLMs.. is it possible to duplicate these in Verilog?

    Thanks
    Abraham

  5. Hi Tiksan,
    Thanks very much for you share,
    and It’s very useful,
    wish you and your blog have a great progress.
    I have read the above books that you said,
    but I still can not write these beautiful code,
    just like you,
    cause I can not organize the mind or code,
    so, can you help me?
    thanks again!

    best regards!
    Trace

  6. Hi Tiksan,
    Just about the study progress that your own,
    and as a new man,
    how to study it,
    thanks a lot!
    Trace

  7. Hi Trace,
    In this case I can only suggest you to look at the examples and ask a lot of questions(here or on the verification forums).
    Download OVM/VMM and look how the code is organised there.
    Bests,
    Tiksan

  8. Thank you for your blog.It is very useful for me. I am new to system verilog and uvm.
    could you please share some projects or materials in uvm.

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