Comments on: Welcome

By: Tiksan

Tiksan — Tue, 15 Mar 2011 16:27:52 +0000

Hi Trace,
In this case I can only suggest you to look at the examples and ask a lot of questions(here or on the verification forums).
Download OVM/VMM and look how the code is organised there.
Bests,
Tiksan

By: Trace

Trace — Wed, 09 Mar 2011 14:14:24 +0000

Hi Tiksan,
Just about the study progress that your own,
and as a new man,
how to study it,
thanks a lot!
Trace

By: Tiksan

Tiksan — Wed, 09 Mar 2011 11:51:14 +0000

Hi Trace,

How can I help you?

By: Trace

Trace — Tue, 08 Mar 2011 14:52:46 +0000

Hi Tiksan,
Thanks very much for you share,
and It’s very useful,
wish you and your blog have a great progress.
I have read the above books that you said,
but I still can not write these beautiful code,
just like you,
cause I can not organize the mind or code,
so, can you help me?
thanks again!

best regards!
Trace

By: Abraham

Abraham — Thu, 16 Dec 2010 13:31:21 +0000

Hi,

This site is really good. I was looking to write VIPs and they’re already here. I need to know how to write VIPs that can be translated into any language.. eg verilog, SystemC, SystemVerilog. How do I get started writing VIPs?

Can we implement queues, command FIFOs and FIFO interfaces in Verilog like the ones in SystemC?? SysC has TLMs.. is it possible to duplicate these in Verilog?

Thanks
Abraham

By: Jimmy

Jimmy — Tue, 31 Aug 2010 09:03:37 +0000

Thanks for sharing.
Your kindness to answer our questions impresses me very much.

By: Tiksan

Tiksan — Fri, 02 Apr 2010 14:37:00 +0000

Hi Ash,

Check the links below:

http://verificationguild.com/
http://www.edaboard.com/

You will find a lot of useful information there.

Bests,
Tiksan.

By: ash

ash — Thu, 01 Apr 2010 20:43:16 +0000

Can you share some interview question and tips on verification, that is expected from 1-2 year experience candidate.It will be a great help.
ash

By: yiyi

yiyi — Fri, 05 Mar 2010 17:09:33 +0000

Very nice blog. Thanks for sharing.

By: Tiksan

Tiksan — Sun, 03 Jan 2010 16:04:56 +0000

Hi zula,

You can start with the following book:

“SystemVerilog for Verification, by Chris Spear,
Second Edition”.

Then you can read the following book:

“Writing Testbenches using SystemVerilog,
by Janick Bergeron
Synopsys, Inc.”

This will be very good start for you.

Best Regards,
Tiksan.