The Wishbone Verification IP is a simple solution for verification of Wishbone B3 master and slave devices. The provided Wishbone verification package includes master and slave SystemVerilog verification IPs and examples. It will help engineers to quickly create verification environment end test their Wishbone master and slave devices.
You can download the Wishbone Verification IP from Downloads page.
- Free SystemVerilog source code
- Easy integration and usage
- Compliant to Wishbone B3 Protocol
- Operates as a Master or Slave
- Supports 1, 2, 4 and 8 bytes data block size
- Supports single cycle transfers
- Supports wait states injection
- Supports programmable retry and error insertion
- Supports full random timings
- Supports misaligned transfers
- Doesn’t support TAGs
- Doesn’t support Lock signal
- Download Wishbone Verification IP and unpack it.
- If you want to run examples
- Go to the following folder: <unpack_dir>/wishbone_vip/examples/sim
- For VCS type the following command: vcs -f file_list.f -sverilog
- For QuestaSim6.4 type the following command: qverilog -f file_list.f
- Please read the Wishbone Verification IP User Manual.
If you have any questions please don’t hesitate to contact me.
You can also use article comments below to ask your questions, to report about bugs or to tell some ideas for future improvement. Your comments are always welcome!