Wishbone Verification IP

The Wishbone Verification IP is a simple solution for verification of Wishbone B3 master and slave devices. The provided Wishbone verification package includes master and slave SystemVerilog verification IPs and examples. It will help engineers to quickly create verification environment end test their Wishbone master and slave devices.

You can download the Wishbone Verification IP from Downloads page.

Features

  1. Free SystemVerilog source code
  2. Easy integration and usage
  3. Compliant to Wishbone B3 Protocol
  4. Operates as a Master or Slave
  5. Supports 1, 2, 4 and 8 bytes data block size
  6. Supports single cycle transfers
  7. Supports wait states injection
  8. Supports programmable retry and error insertion
  9. Supports full random timings
  10. Supports misaligned transfers

Limitations

  1. Doesn’t support TAGs
  2. Doesn’t support Lock signal

Installation

  1. Download Wishbone Verification IP and unpack it.
  2. If you want to run examples
    1. Go to the following folder: <unpack_dir>/wishbone_vip/examples/sim
    2. For VCS type the following command: vcs -f file_list.f -sverilog
    3. For QuestaSim6.4 type the following command: qverilog -f file_list.f
  3. Please read the Wishbone Verification IP User Manual.

Support

If you have any questions please don’t hesitate to contact me.

You can also use article comments below to ask your questions, to report about bugs or to tell some ideas for future improvement. Your comments are always welcome!

4 thoughts on “Wishbone Verification IP

  1. Hi,

    Thanks for your works for “Wishbone Verification IP”.
    It is very helpful for me.

    How about to support Wishbone B4 version that
    contains pipeline transfer hand-shaking?

  2. Hi kaku817,

    Thank you very much for informing me about Wishbone B4.
    I will find the time to implement this new version.
    Bests Tiksan.

  3. Hello,

    Good job, this is very helpfull.

    I got an error with your slave interface asserting “ack_o” and “rty_o” during the same cycle.

    (this is not allowed : rule 3.45)

    A suggested correction in wshsb_s.sv line 166:

    end else if((this.rtyNum != rtyCnt) && (this.tr.address == this.rtyAddr)) begin
    this.ifc.cb_n.rty_o <= 1'b1;
    this.ifc.cb_n.ack_o <= 1'b0;
    rtyCnt++;
    end else begin

  4. Good catch Mathieu. Thank you very much.

    Your correction should work(but I did not try yet).
    And the same correction can be applied for err_o signal generation as well.

    Best Regards,
    Tiksan

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